1. Field of the Invention
The field of the invention relates generally to multiplexers, and more particularly, multiplexers used for high-speed transmission.
2. Discussion of the Related Art
The current high-growth nature of digital communications demands higher speed serial communication circuits. Present day technologies barely manage to keep up with the present need to communicate at high speeds, e.g. gigabit, terabit, and higher transmission speeds. New techniques are needed to ensure that methods for serial communication can continue to expand and grow.
Multiplexers are typically used in communication systems to multiplex lower rate data signals onto a higher rate channel. Examples of communication systems include optical communication systems (e.g. SONET communication systems) which multiplex multiple data streams onto a single channel in a serial manner. Other communication system types also use multiplexers, such as communication devices that operate in LANs, internal communication systems of a computer system, processors of a multiprocessor system, and the like.
According to one embodiment of the invention, a multiplexer is provided that is symmetric in that substantially the same delay is experienced from any input of the multiplexer to any multiplexer output. According to one aspect of the invention, it is realized that in conventional serial transmission systems, standard Current Mode Logic (CML) multiplexers are used which are asymmetric and exhibit different delays between select and data inputs. Because of these delays, conventional transmission systems experience jitter at high frequencies. More particularly, it is-realized that time differences between a transition on a select input of a multiplexer and a transition of a data input of the multiplexer produce a temporal offset in subsequent transitions of the output of the multiplexer. To extend the operable range of communication systems, a symmetric multiplexer may be used which has substantially the same delay from any input to the multiplexed output, thus reducing jitter. Further, it is realized that it would be beneficial to produce a multiplexer that presents the same loading characteristics to each data input and select line of the multiplexer.
For example, the multiplexer may be part of a communication system having a serial data transmission circuit. More particularly, there are conventional serial data transmission circuits that utilize an output retiming circuit, and require clocking at the same frequency as the output bit rate. At bit rates above, for example, 10 Gb/s, this conventional method becomes prohibitive, because of the lack of Voltage Controlled Oscillators (VCOs) capable of operating at this speed. A symmetric multiplexer architecture addresses the issue by utilizing ring oscillators which are not available with typical LC tanks. The multi-phase nature of ring oscillators enables the serial data transmission circuit to use a clock frequency, for example, of one-quarter the 20 Gb/s bit rate, or 5 GHz. This example communication technique implements two signals in quadrature from a VCO.
According to one aspect of the invention, a multiplexer is provided comprising data, select, and output terminals, wherein a first delay between the select and output terminals is substantially identical to a second delay measured between the data and output terminals. According to another embodiment of the invention, the multiplexer further comprises a first and second symmetric half, each half including a differential current switch for each of a first and second input terminals and the select terminals, and wherein each of the first and second halves is associated with a first and second output, the first and second output being complimentary signals.
According to another embodiment of the invention, load measured from the data and select terminals is substantially identical. According to another embodiment of the invention, each differential current switch is coupled to a current switch comprising a plurality of transistors, wherein each of the differential current switches is adapted to remove a unit of current from at least one of the plurality of transistors.
According to another embodiment of the invention, each of the differential current switches is coupled to the current switch by a respective input line, and wherein for each transition on any one of the first and second input terminals, a current measured on each of the respective input lines does not change by more than one unit of current.
According to another embodiment of the invention, each of the differential current switches is coupled to the current switch by a respective input line, and wherein for each transition on both of the first and second input terminals, a current measured on each of the respective input lines does not change by more than one unit of current.
According to another embodiment of the invention, each of the differential current switches is coupled to the current switch by a respective input line, and wherein for each transition on both the select terminal and at least one of the first and second input terminals, a current measured on each of the respective input lines does not change by more than one unit of current.
According to another embodiment of the invention, the current switch includes at least four input lines, and wherein each of the four input lines is coupled to at least two of the differential current switches, and wherein the at least two of the differential current switches is configured to remove at least one of zero, one, and two units of current from a respective input line.